1. Field of Invention
Embodiments exemplarily described herein generally relate to semiconductor packages and methods of manufacturing the same. More particularly, embodiments exemplarily described herein relate to semiconductor packages having increased adhesive strength between the components within the semiconductor packages such as an encapsulation material, redistribution patterns and/or a dielectric material, and to methods of manufacturing the same. Other embodiments exemplarily described herein relate to semiconductor packages having increased interconnection characteristics and reliability, and to methods of manufacturing the same.
2. Description of the Related Art
In the semiconductor industry, integrated circuit (IC) packaging technologies continue to develop to meet the demand for scaling down of size, high density and improved mounting reliability.
Package stacking technology and chip stacking technology are examples of such IC packaging technologies. In the package stacking technology, semiconductor packages typically are stacked using solder balls. In the chip stacking technology, semiconductor chips are typically stacked using plugs formed through the semiconductor chips.
In particular, the semiconductor chip typically includes a plurality of pad areas disposed on an active surface thereof. The solder balls are generally connected to the pad areas. However, following the decrease in design rules, the need for high pin count packages, and a smaller pad pitch, according to recent trends in the electronics industry, it can be difficult to ensure that adjacent solder balls do not contact each other.
Consequently, fan-out type semiconductor packages have been developed. A typical fan-out type semiconductor package includes a plurality of redistribution patterns formed over the active surface of the semiconductor chip that electrically redistribute the locations of the pad areas on the active surface of the semiconductor chip to regions outside an area defined by the active surface of the semiconductor chip.
In a typical fan-out type semiconductor package, the redistribution patterns are arranged over the active area of the semiconductor chip and are attached to the encapsulation material that encapsulates the semiconductor chip. The redistribution patterns can be formed by, for example, forming an interlevel dielectric (ILD) over the encapsulation material. Then, the ILD is patterned to form a groove therein. Next, a conductive material is formed over the resulting structure and within the groove to form the redistribution patterns.
However, the ILD is susceptible to delamination from the encapsulation material because the ILD is typically very thin and as a result, the interface between the encapsulation material and the ILD can be vulnerable to physical impacts or moisture or stress. Furthermore, for the same reason, the redistribution patterns can also be susceptible to delamination from the encapsulation material.
In addition, multi-chip packages (i.e., semiconductor packages incorporating a plurality of stacked semiconductor chips or packages) can be formed by patterning encapsulation material to create an opening enabling electrical connections to external terminals. The encapsulation material can be patterned via a laser drilling process using an infrared (IR) laser. IR lasers have a relatively long wavelength. Accordingly, light emitted by IR lasers during the laser drilling process is scattered as it passes through the encapsulation material. As a result, sidewalls of the opening in the encapsulation material can become damaged which, in turn, leads to poor adhesion between a subsequently formed conductive pattern therein and the encapsulation material.
These and other problems are addressed by the embodiments of the present invention exemplarily described herein.